Technology scaling has enabled the number of cores within a System on Chip to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. Typically, the interfaces between these clock domains experience multi-cycle latency due to their use of “brute force” synchronizers. Improvements in system performance can be achieved by replacing these brute force synchronizers with predictive synchronizers, which experience less than a cycle of latency. Unfortunately, the predictive synchronizers proposed so far require high power delay lines, rationally related clocks, or over a thousand cycles of latency for every change in frequency. Here we present a modified predictive synchronizer without these limitations. Our techniques allow for uninterrupted data flow during gradual frequency change and only a 20 cycle pause in data flow after an instant frequency change. In addition, we present an alternative clock domain interface which achieves less than a cycle of latency with an average 15% reduction in throughput.