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Predictive Periodic Synchronization Using Phase-Locked Loop Digital Ratio Updates



Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.